(1) Field of the Invention
The invention relates to the manufacture of highly dense integrated circuits, and more particularly to input protection devices to protect attached integrated circuits from damage due to electrostatic discharge.
(2) Description of the Related Art
During handling and operation of integrated circuit devices using Field Effect Transistor (FET) technology, large electrostatic charges can be transferred from external contacts of the integrated circuit into the interior of the circuit, causing damage and/or destruction to FET devices within. In order to prevent such damage, workers in the field have added input protection devices which are typically located between the external contacts and the FET devices. These protection devices are designed to provide a path to safely discharge the electrostatic charge and prevent damage to the internal FET devices.
One such device is shown in U.S. Pat. No. 5,142,345 by Miyata. In this invention, an input protection device is formed and later connected to an internal FET device and a memory structure, which it is designed to protect from electrostatic discharge (ESD). The input protection device is itself an FET device. The protection device's source/drain regions are formed with a single heavy ion implant during separate processing steps from the formation of the source/drain regions for the connected internal devices. Spacers are formed on the gates of both the internal and the protection devices, since the internal devices are formed using LDD (lightly doped drain) regions that require the spacers form one ion implant step.
Another such device is shown in U.S. Pat. No. 5,077,590 by Fujihira, and consists of a high voltage semiconductor device with an integrated Zener diode.